1. Field of the Invention
The present invention relates to a device for interconnecting the nodes a computer system composed of a plurality of central processing unit (CPU) nodes and a method thereof. More particularly, it relates to a peripheral component interconnect (PCI)-express switch used to interconnect nodes in a computer system in which a plurality of CPU nodes are connected by the PCI-express bus, which is a high-speed serial bus, and a control device thereof.
2. Description of the Related Art
With the recent development of the digitization of data, the amount of data to be processed by a computer system has continued to rapidly increase. In order to cope with this request, an interconnect technology for internally connecting the computer system has also continued to progress so as to enable high-speed and large-capacity data transfer.
Although conventionally a PCI bus has been widely used for an interconnect function inside a computer system, a serial type interconnect function whose installation cost is low despite its high speed and large capacity will become a mainstream in the near future. In particular, a PCI-express bus, which is a serial type interconnect function worked out as the successor of the PCI bus by special interest group (SIG) is expected to be widely used in various types of computer systems ranging from a desk-top personal computer (PC) to a large-scaled server and a storage device.
FIG. 1A shows the configuration of a conventional computer system using a PCI bus. The computer system shown in FIG. 1A comprises a CPU 11, a memory controller (MCH) 12, a plurality of pieces of memory 13-1˜13-4 and an I/O controller (ICH) 14. The I/O controller 14 comprises a plurality of PCI buses, and a card mounting a PCI device can be mounted in PCI slots 15-1˜15-4.The operational frequency of the PCI bus is 33˜133 MHz, and has two types of bus width, 32 bits and 64 bits. The maximum bandwidth per slot of the bus is 1 GB/s in total for both directions.
In FIG. 1B, a PCI-express bus is used instead of the PCI bus shown in FIG. 1A. The computer system shown in FIG. 1B comprises a CPU 11, a memory controller 12 and memory 13-1˜13-4. The memory controller 12 comprises a plurality of PCI-express buses, and a card mounting a PCI device can be mounted in PCI slots 16-1˜16-4. The maximum bandwidth per slot of the bus is 1 GB/s for each direction.
The PCI-express bus, which is a serial bus, has a less number of signals than the PCI bus, which is a parallel bus. Therefore, the PCI-express bus has the effect of reducing the cost of hardware. For example, the number of chip sets can be reduced, the number of wires on a board can be reduced and a smaller connector can be used. Simultaneously, since bandwidth more than double of the PCI bus can be provided, the request for high speed and high performance can be satisfied.
In a system composed of a plurality of computers and a plurality of peripheral devices, a hub box capable of arbitrarily selecting peripheral devices used by each computer is also known (for example, see Patent reference 1).
Patent Reference 1:
Japanese Patent Application No. 2001-229119
As described above, the PCI-express bus is expected to be used in a wide field as a high-performance and low-cost interconnect function. However, since the PCI-express bus theoretically follows the architecture of the PCI bus, it has the following problems if it is used to connect a plurality of CPU nodes.
FIG. 1C shows the configuration of a virtual computer system in which CPU nodes 21-1˜21-8 having the configuration shown in FIG. 1B are connected by a PCI-express switch 22 with a plurality of ports. In the specification of the PCI-express bus, one port of the switch 22 is called an upstream port, and plays a special role of initializing the entire system or the like. Therefore, a specific CPU node connected to the upstream port of the switch 22 occupies a privileged position, and the switch 22 cannot operate without this CPU node.
However, in a server or a storage device which is composed of a plurality of CPU nodes, each CPU node sometime is used as an extendable unit depending on its product configuration in order to improve the flexibility of a product. In this case, the PCI-express switch cannot operate without the specific CPU node, and as a result, the system cannot operate. Such a situation must be avoided.